1. Field of the Invention
This invention relates to improvements in circuitry and methods useful in mass data storage devices, or the like, and more particularly, to improvements in circuitry and methods for controlling gain variations in a reader amplifier used in amplifying signals of an MR head, or the like, in a hard disk drive system.
2. Relevant Background
Mass data storage devices include, for example, hard disk drives, CD-ROM devices, DVD devices, high capacity floppy disk devices, tape drives and other magnetic recording storage devices, and optical storage devices or like family of devices onto which data is recorded for storage and subsequent retrieval. Hard disk drives, for instance, may be used in many applications, including personal computers, set top boxes, video and television applications, audio applications, or some mix thereof. Applications for hard disk drives are still being developed, and are expected to further increase in the future.
Typically, the data transducer used in mass data storage devices, whether optical or magnetic, produce an analog output signal that is detected and processed to reproduce the data that is recorded on the data recording media. The analog signal is generally amplified by an open loop amplifier to produce an amplified signal for data detection and processing.
One classic open-loop amplifier design that has been used has a bipolar input gain stage. Typically, such amplifier is biased with a current that is equal to a PTAT (Proportional to Absolute Temperature) voltage divided by a resistance, for instance, that may be provided by an internal or on-chip resistor (Rint). This is intended to generally maintain the gain of the stage despite process and temperature variations.
Recently, MOS input stage amplifier designs have been becoming more popular. However, low voltage designs using MOS input gain stage require different biasing methods. In a conventional MOS input stage design, a PTAT/Rint current may still be used for biasing. The internal resistance, Rint, is typically provided by a resistance internal to the gain stage, for instance, as an integrated circuit resistance, and is referred to herein as a reference resistor. Such a design, however, may have greater than ±20% of gain variations due to process and temperature variations. Alternatively, using a current that is equal to a bandgap reference voltage divided by the internal resistance, Rint, may have even larger gain variations, which may, in fact, exceed ±30%.
Nevertheless, users of such amplifiers often have strict design requirements. It is not unusual to have gain variation specification limits that are less than or equal to 20%. Consequently, in order to meet these specifications, IC vendors typically resort to expensive fuse trimming techniques to remove the process variation contributions to the gain variations. Once the process variations have been controlled, the remaining gain movement due to temperature variations is then generally less than 20%, thereby meeting the specification requirement.
One of the undesired results of large gain variations in low voltage reader amplifiers is that noise referred at the amplifier input is affected by the gain changes resulting from the stabilization technique for process and temperature variations. Thus, as the gain changes, for example, by decreasing, for such process and temperature variations, the noise at the input of the amplifier also increases. This makes adherence to the ±20% specification difficult over the range of temperature and process variations expected.
One circuit 10 that has been proposed is shown in FIG. 1, to which reference is now made. The CMOS core circuit 10 includes a first stage cascade amplifier 11 that includes an input transistor 12 to the gate of which the input signal, Vin, is applied on line 13 and a cascode transistor 14 connected in series with the input transistor 12 in a cascode configuration. A constant bias voltage, Vcas, is connected to the gate of the cascode transistor 14, which serves to reduce the amplifier input capacitance by reducing the Miller capacitance of the drain of transistor 12 when it is referred back to the amplifier input. The cascode transistor 14 improves the frequency response of the amplifier.
A current source 16 is connected in series with transistors 12 and 14 between a voltage supply line 17, Vdd, and a ground line 19, and a resistor 18 is connected between the input line 13 and the drain of the control transistor 14. A load element, such as the load resistor 20 shown, is connected between the drain of the control transistor 14 and the output node 22. A current source 24 and an output transistor 26 are connected n series between the supply line 17 and ground line 19, the junction node 22 therebetween providing the output from the circuit 10.
An extension of the circuit 10 of FIG. 1 is shown in FIG. 2, to which reference is now additionally made, which shows a BiCMOS circuit embodiment 30. The circuit elements in the BiCMOS circuit embodiment 30 may be the same as those of the all CMOS circuit embodiment 10, except that the output amplifier transistor 32 may be an npn bipolar transistor. The operation of the BiCMOS circuit embodiment 30 of FIG. 2 is essentially the same as that of the all CMOS circuit embodiment 10 of FIG. 1, except that the substitution of the bipolar transistor 32 for the MOS transistor 26 produces a greater frequency bandwidth in the circuit 30. In the circuit 30, the value of the current source 24′ may be PTAT/Rint to control the input resistance of the circuit. In the circuit embodiments shown, Rint is not specifically shown, but may be provided by a reference resistor on the same integrated circuit chip onto which the remaining circuitry is also constructed. Nevertheless, one of the goals in the design of the circuits according to the invention is to establish a circuit in which the terms in the current equations are inversely proportional to the product of this resistance squared, the carrier mobility, and the oxide capacitance.
What is needed, therefore, is an MOS input stage amplifier design that does not require expensive fuse trimming techniques, yet still has low gain variations over a wide range of temperature variations.